AC82G41SLGQ3 Datasheet, PDF (485/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2.20 IOTLB_REG—IOTLB Invalidate Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
108-10Fh
0000000000000000h
R/W, RO
64 bits
This register is used to control page-table entry caching. The act of writing the upper
byte of the IOTLB_REG with IVT field set causes the hardware to perform the IOTLB
invalidation. There is an IOTLB_REG for each IOTLB Invalidation unit supported by
hardware.
Bit
Access
Default
Value
RST/PWR
Description
Invalidate IOTLB (IVT): Software requests IOTLB
invalidation by setting this field. Software must also set the
requested invalidation granularity by programming the
IIRG field.
Hardware clears the IVT field to indicate the invalidation
request is complete. Hardware also indicates the
granularity at which the invalidation operation was
performed through the IAIG field. Software must not
submit another invalidation request through this register
while the IVT field is set, nor update the associated
Invalidate Address register.
63
R/W
0
Core
Software must not submit IOTLB invalidation requests
through any of the IOTLB invalidation units when there is a
context-cache invalidation request pending at this DMA-
remapping hardware unit.
When more than one IOTLB invalidation units are
supported by a DMA-remapping hardware unit, software
may submit IOTLB invalidation request through any of the
currently free units while there are pending requests on
other units.
Hardware implementations reporting write-buffer flushing
requirement (RWBF=1 in Capability register) must
implicitly perform a write buffer flushing before reporting
invalidation complete to software through the IVT field.
Datasheet
485