AC82G41SLGQ3 Datasheet, PDF (281/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.7
CLS—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
Ch
00h
RO
8 bits
The IGD does not support this register as a PCI slave.
Bit
7:0
9.1.8
Access
RO
Default
Value
00h
RST/PWR
Description
Core
Cache Line Size (CLS): This field is hardwired to 0s. The
IGD as a PCI compliant master does not use the Memory
Write and Invalidate command and, in general, does not
perform operations based on cache line size.
MLT2—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
Dh
00h
RO
8 bits
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
Bit
7:0
9.1.9
Access
RO
Default
Value
00h
RST/PWR
Description
Core
Master Latency Timer Count Value (MLTCV): Hardwired
to 0s.
HDR2—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
Eh
80h
RO
8 bits
This register contains the Header Type of the IGD.
Bit
Access
Default
Value
RST/PWR
Description
7
RO
6:0
RO
Multi Function Status (MFUNC): This bit indicates if the
device is a Multi-Function Device. The Value of this
1b
Core
register is determined by Device #0, offset 54h,
DEVEN[4]. If Device 0 DEVEN[4] is set, the MFUNC bit is
also set.
Header Code (H): This is a 7-bit value that indicates the
00h
Core
Header Code for the IGD. This code has the value 00h,
indicating a type 0 configuration space format.
Datasheet
281