AC82G41SLGQ3 Datasheet, PDF(82/604 Page) Intel Corporation – Intel® 4 Series Chipset Family

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AC82G41SLGQ3 Datasheet, PDF (82/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

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Register Description

4.4.2.2

4.5

4.5.1

DMI Configuration Accesses

Accesses to disabled (G)MCH internal devices, bus numbers not claimed by the Host-

PCI Express bridge, or PCI Bus 0 devices not part of the (G)MCH will subtractively

decode to the ICH10/ICH7 and consequently be forwarded over the DMI via a PCI

Express configuration TLP.

If the Bus Number is zero, the (G)MCH will generate a Type 0 Configuration Cycle TLP

on DMI. If the Bus Number is non-zero, and falls outside the range claimed by the

Host-PCI Express bridge, the (G)MCH will generate a Type 1 Configuration Cycle TLP on

DMI.

The ICH10/ICH7 routes configurations accesses in a manner similar to the (G)MCH. The

ICH10/ICH7 decodes the configuration TLP and generates a corresponding

configuration access. Accesses targeting a device on PCI Bus 0 may be claimed by an

internal device. The ICH10/ICH7 compares the non-zero Bus Number with the

Secondary Bus Number and Subordinate Bus Number registers of its PCI-to-PCI

bridges to determine if the configuration access is meant for Primary PCI, or some

other downstream PCI bus or PCI Express link.

Configuration accesses that are forwarded to the ICH10/ICH7, but remain unclaimed by

any device or bridge will result in a master abort.

I/O Mapped Registers

The (G)MCH contains two registers that reside in the processor I/O address space â the

Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data

(CONFIG_DATA) Register. The Configuration Address Register enables/disables the

configuration space and determines what portion of configuration space is visible

through the Configuration Data window.

CONFIG_ADDRESSâConfiguration Address Register

I/O Address:

Default Value:

Access:

Size:

0CF8h Accessed as a DWord

00000000h

R/W

32 bits

CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DWord. A Byte or

Word reference will "pass through" the Configuration Address Register and DMI onto

the Primary PCI bus as an I/O cycle. The CONFIG_ADDRESS register contains the Bus

Number, Device Number, Function Number, and Register Number for which a

subsequent configuration access is intended.

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Datasheet

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