AC82G41SLGQ3 Datasheet, PDF (76/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Register Description
4.1
Register Terminology
The following table shows the register-related terminology that is used.
Item
RO
RO/S
RS/WC
R/W
R/WC
R/WC/S
R/W/K
R/W/L
R/W/S
R/W/SC
Definition
Read Only bit(s). Writes to these bits have no effect. This may be a status bit
or a static value.
Read Only / Sticky bit(s). Writes to these bits have no effect. These are status
bits only. Bits are not returned to their default values by "warm" reset, but will
be reset with a cold/complete reset (for PCI Express related bits a cold reset is
“Power Good Reset” as defined in the PCI Express spec).
Read Set / Write Clear bit(s).The first time the bit is read with an enabled
byte, it returns the value 0, but a side-effect of the read is that the value
changes to 1. Any subsequent reads with enabled bytes return a 1 until a 1 is
written to the bit. When the bit is read, but the byte is not enabled, the state
of the bit does not change, and the value returned is irrelevant, but will match
the state of the bit.
When a 0 is written to the bit, there is no effect. When a 1 is written to the bit,
its value becomes 0, until the next byte-enabled read. When the bit is written,
but the byte is not enabled, there is no effect.
Read / Write bit(s). These bits can be read and written by software. Hardware
may only change the state of this bit by reset.
Read / Write Clear bit(s). These bits can be read. Internal events may set this
bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding bit(s) and a
write of ‘0’ has no effect.
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may
set this bit. A software write of ‘1’ clears (sets to ‘0’) the corresponding bit(s)
and a write of ‘0’ has no effect. Bits are not cleared by "warm" reset, but will
be reset with a cold/complete reset (for PCI Express related bits a cold reset is
“Power Good Reset” as defined in the PCI Express spec).
Read / Write / Key bit(s). These bits can be read and written by software.
Additionally this bit, when set, prohibits some other bit field(s) from being
writeable (bit fields become Read Only).
Read / Write / Lockable bit(s). These bits can be read and written by software.
Additionally, there is a Key bit (which is marked R/W/K or R/W/L/K) that,
when set, prohibits this bit field from being writeable (bit field becomes Read
Only).
Read / Write / Sticky bit(s). These bits can be read and written by software.
Bits are not cleared by "warm" reset, but will be reset with a cold/complete
reset (for PCI Express related bits a cold reset is “Power Good Reset” as
defined in the PCI Express spec).
Read / Write / Self Clear bit(s). These bits can be read and written by
software. When the bit is 1, hardware may clear the bit to ‘0’ based upon
internal events, possibly sooner than any subsequent software read could
retrieve a 1.
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Datasheet