AC82G41SLGQ3 Datasheet, PDF (318/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
Bit
Access
Default
Value
RST/PWR
Description
4
RO
3
RO
1b
Core
Capabilities List (CL): Indicates the presence of a
capabilities list, hardwired to 1.
0b
Core
Interrupt Status (IS): Indicates the interrupt status of
the device (1 = asserted).
2:0
RO
000b
Core
Reserved
10.1.4
RID— Revision ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
8h
see description below
RO
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
see
description
Core
Revision ID (RID): Indicates stepping of the HECI host
controller. Refer to the Intel^® 4 Series Chipset Family
Specification Update for the value of this register.
10.1.5
CC— Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/0/PCI
9-Bh
0C8001h
RO
24 bits
Bit
23:16
15:8
7:0
Access
RO
RO
RO
Default
Value
0ch
80h
01h
RST/PWR
Description
Core
Core
Core
Base Class Code (BCC): This field indicates the base
class code of the HECI host controller device.
Sub Class Code (SCC): This field indicates the sub class
code of the HECI host controller device.
Programming Interface (PI): This field indicates the
programming interface of the HECI host controller device.
318
Datasheet