AC82G41SLGQ3 Datasheet, PDF (280/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.5
RID2—Revision Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
8h
see description below
RO
8 bits
This register contains the revision number for Device 2, Functions 0 and 1.
Bit
7:0
9.1.6
Access
RO
Default
Value
see
description
RST/PWR
Description
Core
Revision Identification Number (RID): This is an 8-bit
value that indicates the revision identification number for
the GMCH Device 0. Refer to the Intel^® 4 Series Chipset
Family Specification Update for the value of this register.
CC—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
9-Bh
030000h
RO
24 bits
This register contains the device programming interface information related to the Sub-
Class Code and Base Class Code definition for the IGD. This register also contains the
Base Class Code and the function sub-class in relation to the Base Class Code.
Bit
Access
Default
Value
23:16
RO
03h
15:8
RO
00h
7:0
RO
00h
RST/
PWR
Core
Core
Core
Description
Base Class Code (BCC): This is an 8-bit value that
indicates the base class code for the GMCH. This code has
the value 03h, indicating a Display Controller.
When MCHBAR offset 44h, bit 31 is 0 this code has the
value 03h, indicating a Display Controller.
When MCHBAR offset 44, bit 31 is 1 this code has the value
04h, indicating a Multimedia Device.
Sub-Class Code (SUBCC): When MCHBAR offset 44 bit
31 is 0 this value will be determined based on Device 0
GGC register, GMS and IVD fields.
00h = VGA compatible
80h = Non VGA (GMS = "0000" or IVD = "1")
When MCHBAR offset 44 bit 31 is 1 this value is 80h,
indicating other multimedia device.
Programming Interface (PI): When MCHBAR offset 44,
bit 31 is 0 this value is 00h, indicating a Display Controller.
When MCHBAR offset 44, bit 31 is 1 this value is 00h,
indicating a NOP.
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Datasheet