AC82G41SLGQ3 Datasheet, PDF (376/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.7.2
IDASR—IDE Alternate status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR1
2h
00h
RO/V
8 bits
Reset: This is not a physical register hence no reset associated with it.
This register implements the Alternate Status register of the Control block of the IDE
function. This register is a mirror register to the status register in the command block.
Reading this register by the HOST does not clear the IDE interrupt of the DEV selected
device
Host read of this register when DEV=0 (Master), Host gets the mirrored data of
IDESD0R register.
Host read of this register when DEV=1 (Slave), host gets the mirrored data of IDESD1R
register.
Bit
Access
Default
Value
RST/PWR
Description
IDE Alternate Status Register (IDEASR): This field
7:0
RO/V
00h
Core
mirrors the value of the DEV0/ DEV1 status register,
depending on the state of the DEV bit on Host reads.
376
Datasheet