AC82G41SLGQ3 Datasheet, PDF (97/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.15
Note:
DEVEN—Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
54-57h
000023DBh
RO, R/W/L
32 bits
Allows for enabling/disabling of PCI devices and functions that are within the (G)MCH.
The table below the bit definitions describes the behavior of all combinations of
transactions to devices controlled by this register.
All the bits in this register are Intel TXT Lockable (82Q45/82Q43 GMCH only).
Bit
31:15
14
Access
RO
R/W/L
Default
Value
00000h
0b
13 (82P45 MCH
only)
R/W/L
1b
13 (82Q45,
82Q43, 82B43,
82G45, 82G43,
82G41, 82P43
(G)MCH only)
12:10
R/W/L
RO
1b
000b
9
R/W/L
1b
8
R/W/L
1b
7
R/W/L
1b
RST/
PWR
Core
Core
Core
Description
Reserved
Reserved
PEG1 Enable (D6EN):
0 = Bus 0, Device 6 is disabled and hidden.
1 = Bus 0, Device 6 is enabled and visible.
Core Reserved
Core
Core
Core
Core
Reserved
EP Function 3 (D3F3EN):
0 = Bus 0, Device 3, Function 3 is disabled and hidden
1 = Bus 0, Device 3, Function 3 is enabled and visible
If Device 3, Function 0 is disabled and hidden, then Device
3, Function 3 is also disabled and hidden independent of
the state of this bit.
If this (G)MCH does not have ME capability (CAPID0[57] =
1 or CAPID0[56] = 1), then Device 3, Function 3 is
disabled and hidden independent of the state of this bit.
EP Function 2 (D3F2EN):
0 = Bus 0, Device 3, Function 2 is disabled and hidden
1 = Bus 0, Device 3, Function 2 is enabled and visible
If Device 3, Function 0 is disabled and hidden, then Device
3, Function 2 is also disabled and hidden independent of
the state of this bit.
If this (G)MCH does not have ME capability (CAPID0[57] =
1 or CAPID0[56] = 1) then Device 3 Function 2 is disabled
and hidden independent of the state of this bit.
EP Function 1 (D3F1EN):
0 = Bus 0, Device 3, Function 1 is disabled and hidden
1 = Bus 0, Device 3, Function 1 is enabled and visible.
If Device 3, Function 0 is disabled and hidden, then Device
3, Function 1 is also disabled and hidden independent of
the state of this bit.
Datasheet
97