AC82G41SLGQ3 Datasheet, PDF (139/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.15
C0ODTCTRL—Channel 0 ODT Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
29C-29Fh
00000000h
RO, R/W
32 bits
Bit
31:12
Access
RO
11:8
R/W
7:4
R/W
3:0
R/W
Default
Value
00000h
0000b
0000b
0000b
RST/PWR
Description
Core
Core
Core
Core
Reserved
DRAM ODT for Read Commands
(sd0_cr_odt_duration_rd): This field specifies the
duration in memory clocks to assert DRAM ODT for Read
Commands. The Async value should be used when the
Dynamic Powerdown bit is set; otherwise, use the Sync
value.
DRAM ODT for Write Commands
(sd0_cr_odt_duration_wr): This field specifies the
duration in memory clocks to assert DRAM ODT for Write
Commands. The Async value should be used when the
Dynamic Powerdown bit is set; otherwise use the Sync
value.
MCH ODT for Read Commands
(sd0_cr_mchodt_duration): This field specifies the
duration in memory clocks to assert (G)MCH ODT for Read
Commands.
5.2.16
C1DRB1—Channel 1 DRAM Rank Boundary Address 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
602-603h
0000h
R/W/L, RO
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
Bit
15:10
9:0
Access
RO
R/W/L
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Channel 1 DRAM Rank Boundary Address 1
(C1DRBA1): See C0DRB1. In stacked mode, if this is the
topmost populated rank in Channel 1, program this value
to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
Datasheet
139