AC82G41SLGQ3 Datasheet, PDF (126/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
2
1
0
5.2.2
Access
R/W/L
R/W/L
R/W
Default
Value
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Ch0 Enhanced Mode (CH0_ENHMODE): This bit
indicates that enhanced addressing mode of operation is
enabled for ch0.
Enhanced addressing mode of operation should be enabled
only when both the channels are equally populated with
same size and same type of DRAM memory.
An added restriction is that the number of ranks/channel
has to be 1, 2, or 4.
NOTE: If any of the two channels is in enhanced mode, the
other channel should also be in enhanced mode.
This bit is locked by ME stolen Memory lock.
Stacked Memory (STKMEM): This bit disables the L
shaped memory configuration. When this bit is set, all the
three channel memory appears as stacked, one above
other.
This bit is locked by ME stolen Memory lock.
EP Present (EPPRSNT): This bit indicates whether EP
UMA is present in the system or not.
This bit is locked by ME stolen Memory lock.
C0DRB0—Channel 0 DRAM Rank Boundary Address 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
200-201h
0000h
R/W/L, RO
16 bits
The DRAM Rank Boundary Registers define the upper boundary address of each DRAM
rank with a granularity of 64 MB. Each rank has its own single-word DRB register.
These registers are used to determine which chip select will be active for a given
address. Channel and rank map:
ch0 rank0:
ch0 rank1:
ch0 rank2:
ch0 rank3:
ch1 rank0:
ch1 rank1:
ch1 rank2:
ch1 rank3:
200h
202h
204h
206h
600h
602h
604h
606h
126
Datasheet