AC82G41SLGQ3 Datasheet, PDF (154/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.38
EPDCYCTRKWRTRD—EPD CYCTRK WRT READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR
A24-A26h
000000h
R/W
24 bits
000h
Bit
23:23
22:20
19:18
Access
RO
R/W
RO
17:14
R/W
13:9
8:6
5:3
2:0
R/W
RO
R/W
RO
Default
Value
0h
000b
0h
0h
00000b
0h
000b
0h
RST/PWR
Description
Core
Core
Core
Core
Reserved
EPDunit DQS Slave DLL Enable to Read Safe
(EPDSDLL2RD): This field provides setting for Read
command safe from the point of enabling the slave DLLs.
Reserved
Min ACT To READ Delayed (C0sd_cr_act_rd): This
field indicates the minimum allowed spacing (in DRAM
clocks) between the ACT and READ commands to the same
rank-bank
Same Rank READ to WRITE Delayed
(C0sd_cr_wrsr_rd): This field indicates the minimum
allowed spacing (in DRAM clocks) between the READ and
WRITE commands.
Reserved
Same Rank Read To Read Delayed
(C0sd_cr_rdsr_rd): This field indicates the minimum
allowed spacing (in DRAM clocks) between two READ
commands to the same rank.
Reserved
154
Datasheet