AC82G41SLGQ3 Datasheet, PDF (69/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
3.7
3.8
Note:
3.8.1
Graphics Memory Address Ranges (Intel^® 82Q45,
82Q43, 82B43, 82G45, 82G43, 82G41 GMCH Only)
The GMCH can be programmed to direct memory accesses to IGD when addresses are
within any of five ranges specified via registers in GMCH’s Device 2 configuration space.
1. The Memory Map Base Register (MMADR) is used to access graphics control
registers.
2. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics
memory allocated via the graphics translation table.
3. The Graphics Translation Table Base Register (GTTADR) is used to access the
translation table.
These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC
address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB
so they do not steal any physical DRAM memory space.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The (G)MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG),
and Top of Memory Segment (TSEG). System Management RAM space provides a
memory area that is available for the SMI handlers and code and data storage. This
memory resource is normally hidden from the system OS so the processor has
immediate access to this memory space upon entry to SMM. The (G)MCH provides
three SMRAM options:
• Below 1 MB option that supports compatible SMI handlers.
• Above 1 MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. For the 82Q45, 82Q43, 82B43,
82G45, 82G43, 82G41 GMCH, TSEG area lies below IGD stolen memory.
The above 1 MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
DMI Interface and PCI Express masters are not allowed to access the SMM space.
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the processor
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing the SMM code. SMM space can be accessed at one of
three transaction address ranges: Compatible, High, and TSEG. The Compatible and
TSEG SMM space is not remapped; therefore, the addressed and DRAM SMM space is
the same address range. Since the High SMM space is remapped the addressed and
DRAM SMM space is a different address range. Note that the High DRAM space is the
same as the Compatible Transaction Address space. Table 8 describes three unique
address ranges:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Datasheet
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