AC82G41SLGQ3 Datasheet, PDF (79/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Register Description
Figure 8.
The PCI Express Enhanced Configuration Mechanism utilizes a flat memory-mapped
address space to access device configuration registers. This address space is reported
by the system firmware to the operating system. There is a register, PCIEXBAR, that
defines the base address for the block of addresses below 4 GB for the configuration
space associated with busses, devices and functions that are potentially a part of the
PCI Express root complex hierarchy. In the PCIEXBAR register there exists controls to
limit the size of this reserved memory mapped space. 256 MB is the amount of address
space required to reserve space for every bus, device, and function that could possibly
exist. Options for 128 MB and 64 MB exist in order to free up those addresses for other
uses. In these cases the number of busses and all of their associated devices and
functions are limited to 128 or 64 busses respectively.
The PCI Express Configuration Transaction Header includes an additional 4 bits
(ExtendedRegisterAddress[3:0]) between the Function Number and Register Address
fields to provide indexing into the 4 KB of configuration space allocated to each
potential device. For PCI Compatible Configuration Requests, the Extended Register
Address field must be all zeros.
Memory Map to PCI Express Device Configuration Space
FFFFFFFh
Bus 255
FFFFFh
Device 31
7FFFh
Function 7
FFFh
PCI Express*
Extended
Configuration
Space
1FFFFFh
Bus 1
FFFFFh
0h
Bus 0
FFFFh
7FFFh
Device 1
Device 0
1FFFh
Function 1
FFFh
Function 0
FFh
PCI
Compatible
Config Space
3Fh
PCI
Compatible
Config Header
Located By PCI
Express* Base
Address
Just the same as with PCI devices, each device is selected based on decoded address
information that is provided as a part of the address portion of Configuration Request
packets. A PCI Express device will decode all address information fields (bus, device,
function and extended address numbers) to provide access to the correct register.
To access this space (steps 1, 2, 3 are done only once by BIOS),
1. Use the PCI compatible configuration mechanism to enable the PCI Express
enhanced configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register.
2. Use the PCI compatible configuration mechanism to write an appropriate PCI
Express base address into the PCIEXBAR register
3. Calculate the host address of the register you wish to set using (PCI Express base
+ (bus number * 1 MB) + (device number * 32KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address)
4. Use a memory write or memory read cycle to the calculated host address to write
or read that register.
Datasheet
79