AC82G41SLGQ3 Datasheet, PDF (169/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.3
EPBAR
Address
Offset
44–47h
50–53h
58–5Fh
60–63h
68–6Fh
Register
Symbol
Register Name
EPESD
EPLE1D
EP Element Self Description
EP Link Entry 1 Description
EPLE1A EP Link Entry 1 Address
EPLE2D EP Link Entry 2 Description
EPLE2A EP Link Entry 2 Address
Default
Value
00000301h
01000000h
0000000000
000000h
02000002h
0000000000
008000h
Access
RO, R/WO
RO, R/WO
RO, R/WO
RO, R/WO
RO
5.3.1
EPESD—EP Element Self Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PXPEPBAR
44-47h
00000301h
RO, R/WO
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
Access
31:24
RO
23:16
R/WO
15:8
RO
7:4
RO
3:0
RO
Default
Value
00h
00h
03h
0h
1h
RST/PWR
Description
Core
Core
Core
Core
Core
Port Number (PN): This field specifies the port number
associated with this element with respect to the
component that contains this element. A value of 00h
indicates to configuration software that this is the default
egress port.
Component ID (CID): This field identifies the physical
component that contains this Root Complex Element.
Number of Link Entries (NLE): This field indicates the
number of link entries following the Element Self
Description. This field reports 3 (one each for PEG0, PEG1
and DMI).
Reserved
Element Type (ET): This field indicates the type of the
Root Complex Element. Value of 1h represents a port to
system memory.
Datasheet
169