AC82G41SLGQ3 Datasheet, PDF (163/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.45
TCO—Thermal Calibration Offset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CE2h
00h
R/W/L/K, R/W/L
8 bits
Bit 7 reset to its default by PLTRST#
Bits 6:0 reset to their defaults by MPWROK
Bit
Access
Default
Value
RST/PWR
Description
7
R/W/L/K
0b
6:0
R/W/L
00h
Core
Core
Lock Bit for Catastrophic (LBC): This bit, when written
to a 1, locks the Catastrophic programming interface,
including bits 7:0 of this register and bits 15:0 of TSTTP,
bits 1,7 of TSC 1, bits 3:0 of TSC 2, bits 4:0 of TSC 3, and
bits 0,7 of TST. This bit may only be set to a 0 by a
hardware reset (PLTRST#). Writing a 0 to this bit has no
effect.
Calibration Offset (CO): This field contains the current
calibration offset for the Thermal Sensor DAC inputs. The
calibration offset is a twos complement signed number
which is added to the temperature counter value to help
generate the final value going to the thermal sensor DAC.
This field is Read/Write and can be modified by Software
unless locked by setting bit 7 of this register.
The fuses cannot be programmed via this register.
Once this register has been overwritten by software, the
values of the TCO fuses can be read using the Therm3
register.
Note for TCO operation:
While this is a seven-bit field, the 7th bit is sign extended
to 9 bits for TCO operation. The range of 00h to 3fh
corresponds to 0 0000 0000 to 0 0011 1111. The range of
41h to 7Fh corresponds to 1 1100 001 (i.e, negative 3Fh)
to 1 1111 1111 (i.e, negative 1), respectively.
Datasheet
163