AC82G41SLGQ3 Datasheet, PDF (462/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.2.4
GCMD_REG—Global Command Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIVC1REMAP
18-1Bh
00000000h
RO, W
32 bits
This register controls DMA-remapping hardware. If multiple control fields in this
register need to be modified, software must serialize through multiple writes to this
register.
Bit
Access
Default
Value
RST/PWR
Description
31
W
Translation Enable (TE): Software writes to this field to
request hardware to enable/disable DMA-remapping
hardware.
0 = Disable DMA-remapping hardware
1 = Enable DMA-remapping hardware
Hardware reports the status of the translation enable
operation through the TES field in the Global Status
register.
Before enabling (or re-enabling) DMA-remapping hardware
through this field, software must:
• Setup the DMA-remapping structures in memory
• Flush the write buffers (through WBF field), if write
buffer flushing is reported as required.
• Set the root-entry table pointer in hardware (through
SRTP field).
0b
Core
• Perform global invalidation of the context-cache and
global invalidation of IOTLB
• If advanced fault logging supported, setup fault log
pointer (through SFL field) and enable advanced fault
logging (through EAFL field).
There may be active DMA requests in the platform when
software updates this field. Hardware must enable or
disable remapping logic only at deterministic transaction
boundaries, so that any in-flight transaction is either
subject to remapping or not at all.
Hardware implementations supporting DMA draining must
drain any in-flight translated DMA read/write requests
queued within the root complex before completing the
translation enable command and reflecting the status of
the command through the TES field in the GSTS_REG.
Value returned on read of this field is undefined.
462
Datasheet