AC82G41SLGQ3 Datasheet, PDF (530/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
13.3 PCI Express*
See Section 1.2 for a list of PCI Express features, and the PCI Express Specification for
further details.
This (G)MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for this
functionality are located in Device 1 and Device 6 configuration space and two Root
Complex Register Blocks (RCRBs). The DMI RCRB contains registers for control of the
ICH10/ICH7 attach ports.
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
PCI Express* Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load-store architecture with a flat address space) is maintained to
ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 1.25 GHz (250 MHz internally) results in 2.5 Gb/s
each direction which provides a 250 MB/s communications channel in each direction
(500 MB/s total) that is close to twice the data rate of classic PCI per lane.
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer’s primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry.
13.3.2
Note:
PCI Express* on (G)MCH
The (G)MCH has two PCIe Gen 2.0 controllers to support 1x16 graphics or 2x8 graphics
modes. To support 1x16 and 2x8 graphics the system should incorporate two graphics
ports- Primary port and Secondary port. Each port is a 1x16 physical connector but 1x8
electrically.
Not all of the above configurations are supported on all Intel 4 Series Chipset (G)MCH
components. Refer to Table 1 in Chapter 1 for (G)MCH components supporting specific
features.
On plugging a PCI Express Gen 2.0 1x16 PCIe graphics card into the primary port the
transaction between the (G)MCH and the PCI Express graphics card will take place
along all the 16 PCI Express lanes. When graphic cards are plugged into both the
primary and secondary ports transaction between the (G)MCH and the graphics card
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