AC82G41SLGQ3 Datasheet, PDF (458/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
21:16
RO
15:13
RO
12:8
RO
7
RO
Default
Value
100011b
000b
00010b
0b
RST/PWR
Description
Core
Core
Core
Core
Maximum Guest Address Width (MGAW): This field
indicates the maximum DMA virtual addressability
supported by remapping hardware.
The Maximum Guest Address Width (MGAW) is computed
as (N+1), where N is the value reported in this field. For
example, a hardware implementation supporting 48-bit
MGAW reports a value of 47 (101111b) in this field.
If the value in this field is X, DMA requests to addresses
above 2(x+1)-1 are always blocked by hardware.
Guest addressability for a given DMA request is limited to
the minimum of the value reported through this field and
the adjusted guest address width of the corresponding
page-table structure. (Adjusted guest address widths
supported by hardware are reported through the SAGAW
field).
Reserved
Supported Adjusted Guest Address Widths (SAGAW):
This 5-bit field indicates the supported adjusted guest
address widths (which in turn represents the levels of
page-table walks) supported by the hardware
implementation.
A value of 1 in any of these bits indicates the
corresponding adjusted guest address width is supported.
The adjusted guest address widths corresponding to
various bit positions within this field are:
0 = 30-bit AGAW (2-level page table)
1 = 39-bit AGAW (3-level page table)
2 = 48-bit AGAW (4-level page table)
3 = 57-bit AGAW (5-level page table)
4 = 64-bit AGAW (6-level page table)
Software must ensure that the adjusted guest address
width used to setup the page tables is one of the supported
guest address widths reported in this field.
Caching Mode (CM):
0 = Hardware does not cache not present and erroneous
entries in the context-cache and IOTLB. Invalidations
are not required for modifications to individual not
present or invalid entries. However, any modifications
that result in decreasing the effective permissions or
partial permission increases require invalidations for
them to be effective.
1 = Hardware may cache not present and erroneous
mappings in the context-cache or IOTLB. Any software
updates to the DMA-remapping structures (including
updates to not-present or erroneous entries) require
explicit invalidation.
Hardware implementations are recommended to support
operation corresponding to CM=0.
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Datasheet