AC82G41SLGQ3 Datasheet, PDF (201/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.37
DSTS—Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
AA-ABh
0000h
RO, R/WC
16 bits
This register reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
Bit
15:6
5
4
3
2
1
0
Access
RO
RO
RO
R/WC
R/WC
R/WC
R/WC
Default
Value
000h
0b
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Reserved and Zero: For future R/WC/S implementations;
software must use 0 for writes to bits.
Transactions Pending (TP):
0 = All pending transactions (including completions for
any outstanding non-posted requests on any used
virtual channel) have been completed.
1 = Indicates that the device has transaction(s) pending
(including completions for any outstanding non-posted
requests for all used Traffic Classes).
Reserved
Unsupported Request Detected (URD): When set, this
bit indicates that the Device received an Unsupported
Request. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal
Error Detected bit is set according to the setting of the
Unsupported Request Error Severity bit. In production
systems setting the Fatal Error Detected bit is not an
option as support for AER will not be reported.
Fatal Error Detected (FED): When set, this bit indicates
that fatal error(s) were detected. Errors are logged in this
register regardless of whether error reporting is enabled
or not in the Device Control register. When Advanced Error
Handling is enabled, errors are logged in this register
regardless of the settings of the uncorrectable error mask
register.
Non-Fatal Error Detected (NFED): When set, this bit
indicates that non-fatal error(s) were detected. Errors are
logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
uncorrectable error mask register.
Correctable Error Detected (CED): When set, this bit
indicates that correctable error(s) were detected. Errors
are logged in this register regardless of whether error
reporting is enabled or not in the Device Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
correctable error mask register.
Datasheet
201