AC82G41SLGQ3 Datasheet, PDF (222/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Direct Memory Interface Registers (DMIBAR)
7.5
Bit
31:16
15
14:8
7:0
7.6
Bit
31
30:27
26:24
23:20
19:17
DMIVC0RCAP—DMI VC0 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
10-13h
00000001h
RO
32 bits
Access
RO
RO
RO
RO
Default
Value
0s
0b
00h
01h
RST/PWR
Description
Core
Core
Core
Core
Reserved
Reject Snoop Transactions (REJSNPT):
0 = Transactions with or without the No Snoop bit set
within the TLP header are allowed on this VC.
1 = When Set, any transaction for which the No Snoop
attribute is applicable but is not Set within the TLP
Header will be rejected as an Unsupported Request.
Reserved
Port Arbitration Capability (PAC): Having only bit 0 set
indicates that the only supported arbitration scheme for
this VC is non-configurable hardware-fixed.
DMIVC0RCTL0—DMI VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/DMIBAR
14-17h
800000FFh
RO, R/W
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Access
RO
RO
RO
RO
R/W
Default
Value
1b
0h
000b
0h
000b
RST/PWR
Description
Core
Core
Core
Core
Core
Virtual Channel 0 Enable (VC0E): For VC0, this bit is
hardwired to 1 and read only as VC0 can never be
disabled.
Reserved
Virtual Channel 0 ID (VC0ID): Assigns a VC ID to the
VC resource. For VC0 this is hardwired to 0 and read only.
Reserved
Port Arbitration Select (PAS): This field configures the
VC resource to provide a particular Port Arbitration service.
Valid value for this field is a number corresponding to one
of the asserted bits in the Port Arbitration Capability field of
the VC resource. Because only bit 0 of that field is
asserted.
This field will always be programmed to 1.
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Datasheet