AC82G41SLGQ3 Datasheet, PDF (271/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.53
VC0RSTS—VC0 Resource Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
11A–11Bh
0002h
RO
16 bits
This register reports the Virtual Channel specific status.
Bit
15:2
1
0
Access
RO
RO
RO
Default
Value
0000h
1b
0b
RST/
PWR
Core
Core
Core
Description
Reserved
VC0 Negotiation Pending (VC0NP):
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization
or disabling).
This bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as whenever the
corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state. It is cleared when the link successfully exits the
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the VC
Negotiation Pending fields for that Virtual Channel are cleared in both
Components on a Link.
Reserved
8.54
RCLDECH—Root Complex Link Declaration
Enhanced
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
140–143h
00010005h
RO
32 bits
This capability declares links from this element (PCI Express) to other elements of the
root complex component to which it belongs. See PCI Express specification for link/
topology declaration requirements.
Bit
31:20
19:16
15:0
Access
RO
RO
RO
Default
Value
000h
1h
0005h
RST/
PWR
Core
Core
Core
Description
Pointer to Next Capability (PNC): This is the last capability in the
PCI Express extended capabilities list.
Link Declaration Capability Version (LDCV): Hardwired to 1 to
indicate compliances with the 1.1 version of the PCI Express
specification.
Note: This version does not change for 2.0 compliance.
Extended Capability ID (ECID): Value of 0005h identifies this
linked list item (capability structure) as being for PCI Express Link
Declaration Capability.
Datasheet
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