AC82G41SLGQ3 Datasheet, PDF (140/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.17
C1DRB2—Channel 1 DRAM Rank Boundary Address 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
604-605h
0000h
R/W/L, RO
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
Bit
15:10
9:0
Access
RO
R/W/L
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Channel 1 DRAM Rank Boundary Address 2
(C1DRBA2): See C0DRB2. In stacked mode, if this is the
topmost populated rank in Channel 1, program this value
to be cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
5.2.18
C1DRB3—Channel 1 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
606-607h
0000h
R/W, RO
16 bits
The operation of this register is detailed in the description for the C0DRB0 register.
Bit
15:10
9:0
Access
RO
R/W
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Channel 1 DRAM Rank Boundary Address 3
(C1DRBA3): See C0DRB3. In stacked mode, this will be
cumulative of Ch0 DRB3.
This register is locked by ME stolen Memory lock.
140
Datasheet