AC82G41SLGQ3 Datasheet, PDF (352/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.5.7
MLT—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
Dh
00h
RO
8 bits
This register defines the minimum number of PCI clocks the bus master can retain
ownership of the bus whenever it initiates new transactions.
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
00h
Core
Master Latency Timer (MLT): Not implemented since
the function is in (G)MCH.
10.5.8
PCMDBA—Primary Command Block IO Bar
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
10-13h
00000001h
RO, R/W
32 bits
Reset: Host system Reset or D3->D0 transition of the function
This 8-byte I/O space is used in Native Mode for the Primary Controller's Command
Block ie BAR0
Bit
31:16
15:3
2:1
0
Access
RO
R/W
RO
RO
Default
Value
0000h
0000h
00b
1b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Base Address (BAR): Base Address of the BAR0 I/O
space (8 consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): This bit indicates a
request for I/O space.
352
Datasheet