AC82G41SLGQ3 Datasheet, PDF (53/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
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Note:
System Address Map
The (G)MCH supports 64 GB (36 bit) of host address space and 64 KB+3 of
addressable I/O space. There is a programmable memory address space under the
1 MB region which is divided into regions which can be individually controlled with
programmable attributes such as Disable, Read/Write, Write Only, or Read Only.
Attribute programming is described in the Register Description section. This section
focuses on how the memory space is partitioned and what the separate memory
regions are used for. I/O address space has simpler mapping and is explained near the
end of this section.
References to the Internal Graphics Device (IGD) apply to the 82Q45, 82Q43, 82B43,
82G45, 82G43,and 82G41 GMCH only.
The (G)MCH supports PCI Express* upper pre-fetchable base/limit registers. This
allows the PCI Express unit to claim IO accesses above 36 bit, complying with the PCI
Express Specification. Addressing of greater than 8 GB is allowed on either the DMI
Interface or PCI Express interface. The (G)MCH supports a maximum of 8 GB of DRAM.
No DRAM memory will be accessible above 8 GB.
When running in internal graphics mode, writes to GMADR range linear range are
supported. Write accesses to linear regions are supported from DMI only. Write
accesses to tileX and tileY regions (defined via fence registers) are not supported from
DMI or the PEG port. GMADR read accesses are not supported from either DMI or PEG.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI Express or DMI, or to the internal graphics device (IGD). In the absence
of more specific references, cycle descriptions referencing PCI should be interpreted as
the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device respectively. The (G)MCH
does not remap APIC or any other memory spaces above TOLUD (Top of Low Usable
DRAM). The TOLUD register is set to the appropriate value by BIOS. The reclaim base/
reclaim limit registers remap logical accesses bound for addresses above 4 GB onto
physical addresses that fall within DRAM.
The Address Map includes a number of programmable ranges:
• Device 0
— PXPEPBAR – Egress port registers. Necessary for setting up VC1 as an
isochronous channel using time based weighted round robin arbitration. (4 KB
window)
— MCHBAR – Memory mapped range for internal (G)MCH registers. For example,
memory buffer register controls. (16 KB window)
— PCIEXBAR – Flat memory-mapped address spaced to access device
configuration registers. This mechanism can be used to access PCI
configuration space (0–FFh) and Extended configuration space (100h–FFFh) for
PCI Express devices. This enhanced configuration access mechanism is defined
in the PCI Express specification. (64 MB, 128 MB, or 256 MB window).
— DMIBAR –This window is used to access registers associated with the Direct
Media Interface (DMI) register memory range. (4 KB window)
— GGCGMS – GMCH graphics control register, Graphics Mode Select (82Q45,
82Q43, 82B43, 82G45, 82G43, 82G41 GMCH only). This register is used to
select the amount of main memory that is pre-allocated to support the internal
Datasheet
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