AC82G41SLGQ3 Datasheet, PDF (396/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.9.24 PMCS—PCI Power Management Control and Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/3/3/PCI
CC-CFh
00000000h
RO/V, RO, R/W
32 bits
0000h
Reset: Host System Reset or D3->D0 transition
This register implements the PCI PM Control and Status Register to allow PM state
transitions and Wake up
Note:
NSR bit of this register. All registers (PCI configuration and Device Specific) marked
with D3->D0 transition reset will only do so if the NSR bit reads a 0. If this bit is a 1,
the D3->D0 transition will not reset the registers.
Bit
31:16
15
14:9
8
7:4
Access
RO
RO
RO
RO
RO
3
RO/V
2
RO
1:0
R/W
Default
Value
0h
0b
00h
0b
0h
0b
0b
00b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Reserved
PME Status (PMES): This bit is set when a PME event is
to be requested. Not supported
Reserved
PME Enable (PMEE): Not Supported
Reserved
No Soft Reset (NSR): When set to1, this bit indicates
that devices transitioning from D3hot to D0 because of
PowerState commands do not perform an internal reset.
Configuration Context is preserved. Upon transition from
the D3hot to the D0 Initialized state, no additional
operating system intervention is required to preserve
Configuration Context beyond writing the PowerState bits.
When clear to 0, devices do perform an internal reset upon
transitioning from D3hot to D0 via software control of the
PowerState bits. Configuration Context is lost when
performing the soft reset. Upon transition from the D3hot
to the D0 state, full re-initialization sequence is needed to
return the device to D0 Initialized.
Value in this bit is reflects chicken bit in ME-AUX register
x13900, bit [6] which is as follows:
0 = Device performs internal reset
1 = Device does not perform internal reset
Reserved
Power State (PS): This field is used both to determine
the current power state of the PT function and to set a new
power state. The values are:
00 = D0 state
11 = D3_HOT state
When in the D3_HOT state, the controller's configuration
space is available, but the I/O and memory spaces are not.
Additionally, interrupts are blocked. If software attempts to
write a '10' or '01' to these bits, the write will be ignored.
396
Datasheet