AC82G41SLGQ3 Datasheet, PDF (296/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.33
PMCS—Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
D4-D5h
0000h
RO, R/W
16 bits
Bit
Access
Default
Value
15
RO
0b
14:13
RO
00b
12:9
RO
0h
8
RO
0b
7:2
RO
00h
1:0
R/W
00b
RST/
PWR
Core
Core
Core
Core
Core
FLR,
Core
Description
PME Status (PMESTS): This bit is 0 to indicate that IGD does not
support PME# generation from D3 (cold).
Data Scale (DSCALE): The IGD does not support data register.
This bit always returns 00 when read, write operations have no
effect.
Data Select (DSEL): The IGD does not support data register. This
bit always returns 0h when read, write operations have no effect.
PME Enable (PME_EN): This bit is 0 to indicate that PME#
assertion from D3 (cold) is disabled.
Reserved
Power State (PWRSTAT): This field indicates the current power
state of the IGD and can be used to set the IGD into a new power
state. If software attempts to write an unsupported state to this
field, write operation must complete normally on the bus, but the
data is discarded and no state change occurs. On a transition from
D3 to D0 the graphics controller is optionally reset to initial values.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
9.1.34
SWSMI—Software SMI
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
E0-E1h
0000h
R/W
16 bits
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, Device 2, Function 0 address E0h–E1h must be reserved for
this register.
Bit
15:8
7:1
0
Access
R/W
R/W
R/W
Default
Value
00h
00h
0b
RST/PWR
Description
Core
Core
Core
Software Scratch Bits (SWSB):
Software Flag (SWF): This field is used to indicate caller
and SMI function desired, as well as return result.
GMCH Software SMI Event (GSSMIE): When set, this
bit will trigger an SMI. Software must write a 0 to clear
this bit.
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Datasheet