AC82G41SLGQ3 Datasheet, PDF (157/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
27
26
25:22
21:18
17:14
13:0
Access
R/W
R/W
R/W
R/W
R/W
R/W
Default
Value
0b
0b
0000b
0000b
0000b
001100001
10000b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Refresh Enable (REFEN):
0 = Disabled
1 = Enabled
DDR Initialization Done (INITDONE): This bit indicates
that DDR initialization is complete.
DRAM Refresh Hysterisis (REFHYSTERISIS):
Hysterisis level - Useful for dref_high watermark cases.
The dref_high flag is set when the dref_high watermark
level is exceeded, and is cleared when the refresh count is
less than the hysterisis level. This bit should be set to a
value less than the high watermark level.
0000 = 0
0001 = 1
.......
1000 = 8
DRAM Refresh High Watermark (REFHIGHWM):
When the refresh count exceeds this level, a refresh
request is launched to the scheduler and the dref_high
flag is set.
0000 = 0
0001 = 1
.......
1000 = 8
DRAM Refresh Low Watermark (REFLOWWM): When
the refresh count exceeds this level, a refresh request is
launched to the scheduler and the dref_low flag is set.
0000 = 0
0001 = 1
.......
1000 = 8
Refresh Counter Time Out Value (REFTIMEOUT):
Program this field with a value that will provide 7.8 us at
the memory clock frequency.
At various memory clock frequencies this results in the
following values:
266 MHz -> 820 hex
333 MHz -> A28 hex
400 MHz -> C30 hex
533 MHz -> 104B hex
666 MHz -> 1450 hex
Datasheet
157