AC82G41SLGQ3 Datasheet, PDF (368/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.13 IDCLOR0—IDE Cylinder Low Out Register Device 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
4h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the Host if DEV = 0. ME-Firmware writes to this register at the
end of a command of the selected device. When the host writes to the IDE Cylinder Low
In Register (IDECLIR), this register is updated with that value.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Cylinder Low Out DEV 0. (IDECLO0): Cylinder Low
Out Register for Master Device.
10.6.14 IDCHOR0—IDE Cylinder High Out Register Device 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
5h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the Host if DEVice = 0. ME-Firmware writes to this register at
the end of a command of the selected device. When the host writes to the IDE Cylinder
High In Register (IDECHIR), this register is updated with that value.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Cylinder High Out DEV 0 (IDECHO0): Cylinder
High out register for Master device.
368
Datasheet