AC82G41SLGQ3 Datasheet, PDF (365/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.7
IDESCOR0—IDE Sector Count Out Register Device 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
2h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the HOST interface if DEV = 0. ME-Firmware writes to this
register at the end of a command of the selected device.
When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this
register is updated.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Sector Count Out Dev0 (ISCOD0): Sector Count
register for Master Device ie Device 0.
10.6.8
IDESNOR0—IDE Sector Number Out Register Device 0
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
3h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the Host if DEV = 0. ME-Firmware writes to this register at the
end of a command of the selected device.
When the host writes to the IDE Sector Number In Register (IDESNIR), this register is
updated with that value.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Sector Number Out DEV 0 (IDESNO0): Sector
Number Out register for Master device.
Datasheet
365