AC82G41SLGQ3 Datasheet, PDF (294/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.1.29
MD—Message Data
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
98-99h
0000h
R/W
16 bits
Bit
15:0
Access
R/W
Default
Value
0000h
RST/PWR
Description
FLR, Core
Message Data (MESSDATA): This is the base message
data pattern assigned by system software and used to
handle an MSI from the device.
When the device must generate an interrupt request, it
writes a 32-bit value to the memory address specified in
the MA register. The upper 16 bits are always set to 0. The
lower 16 bits are supplied by this register.
9.1.30
GDRST—Graphics Debug Reset
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/PCI
C0h
00h
RO, R/W/SC, R/W
8 bits
Bit
Access
Default
Value
RST/PWR
Description
7:4
RO
3:2
R/W
1
RO
0
R/W/SC
0h
FLR, Core Reserved
Graphics Reset Domain (GRDOM):
00 = Full Graphics Reset will be performed (both render
and display clock domain resets asserted)
00b
FLR, Core 01 = Render Only Reset (render clock domain reset
asserted)
10 = Reserved (invalid Programming)
11 = Media Only Reset (Media domain reset get asserted)
0b
FLR, Core Reserved
Graphics Reset Enable (GR): Setting this bit asserts
graphics-only reset. The clock domains to be reset are
determined by GRDOM. Hardware resets this bit when the
reset is complete. Setting this bit without waiting for it to
clear, is undefined behavior.
Once this bit is set to a 1, all GFX core MMIO registers are
returned to power on default state. All Ring buffer pointers
are reset, command stream fetches are dropped and
0b
FLR, Core ^{ongoing render pipeline processing is halted, state}
machines and State Variables returned to power on default
state. If the Display is reset, all display engines are halted
(garbage on screen). VGA memory is not available, Store
DWords and interrupts are not ensured to be completed.
Device 2 I/O registers are not available.
Device 2 Configuration registers continue to be available
while Graphics reset is asserted.
This bit is hardwired auto-clear.
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Datasheet