AC82G41SLGQ3 Datasheet, PDF (502/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.3.5
GSTS_REG—Global Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/GFXVTBAR
1C-1Fh
00000000h
RO
32 bits
This register reports general DMA-remapping hardware status.
Bit
Access
Default
Value
RST/PWR
Description
31
RO
30
RO
29
RO
28
RO
27
RO
26
RO
Translation Enable Status (TES): This field indicates the
status of DMA-remapping hardware.
0
Core
0 = DMA-remapping hardware is not enabled
1 = DMA-remapping hardware is enabled
Root Table Pointer Status (RTPS): This field indicates
the status of the root- table pointer in hardware.
This field is cleared by hardware when software sets the
SRTP field in the Global Command register. This field is set
0
Core
by hardware when hardware finishes the set root-table
pointer operation (by performing an implicit global
invalidation of the context-cache and IOTLB, and setting/
updating the root-table pointer in hardware with the value
provided in the Root-Entry Table Address register).
Fault Log Status (FLS): This field is valid only in
implementations supporting advanced fault logging.
This field indicates the status of the fault-log pointer in
hardware. This field is cleared by hardware when software
0
Core
sets the SFL field in the Global Command register. This
field is set by hardware when hardware finishes the set
fault-log pointer operation (by setting/updating the faultlog
pointer in hardware with the value provided in the
Advanced Fault Log register).
Advanced Fault Logging Status (AFLS): This field is
valid only for implementations supporting advanced fault
logging.
0
Core
This field indicates advanced fault logging status.
0 = Advanced Fault Logging is not enabled
1 = Advanced Fault Logging is enabled
Write Buffer Flush Status (WBFS): This bit is valid only
in implementations requiring write buffer flushing.
This field indicates the status of the write buffer flush
0
Core
operation. This field is set by hardware when software sets
the WBF field in the Global Command register. This field is
cleared by hardware when hardware finishes the write
buffer flush operation.
Queued Invalidation Enable Status (QIES): This field
indicates queued invalidation enable status.
0
Core
0 = queued invalidation is not enabled
1 = queued invalidation is enabled
502
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