AC82G41SLGQ3 Datasheet, PDF (206/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.40
LSTS—Link Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
B2-B3h
1000h
R/WC, RO
16 bits
This register indicates PCI Express link status.
Bit
Access
Default
Value
RST/PWR
Description
15
R/WC
0b
14
R/WC
0b
13
RO
0b
12
RO
1b
Core
Core
Core
Core
Link Autonomous Bandwidth Status (LABWS): This bit
is set to 1b by hardware to indicate that hardware has
autonomously changed link speed or width, without the
port transitioning through DL_Down status, for reasons
other than to attempt to correct unreliable link operation.
This bit must be set if the Physical Layer reports a speed or
width change was initiated by the downstream component
that was indicated as an autonomous change.
This bit must be set when the upstream component
receives eight consecutive TS1 or TS2 ordered sets with
the Autonomous Change bit set.
Link Bandwidth Management Status (LBWMS): This
bit is set to 1b by hardware to indicate that either of the
following has occurred without the port transitioning
through DL_Down status:
• A link retraining initiated by a write of 1b to the Retrain
Link bit has completed.
Note: This bit is Set following any write of 1b to the
Retrain Link bit, including when the Link is in the
process of retraining for some other reason.
• Hardware has autonomously changed link speed or
width to attempt to correct unreliable link operation,
either through an LTSSM timeout or a higher level
process
This bit must be set if the Physical Layer reports a speed or
width change was initiated by the downstream component
that was not indicated as an autonomous change.
Data Link Layer Link Active (Optional) (DLLLA): This
bit indicates the status of the Data Link Control and
Management State Machine. It returns a 1b to indicate the
DL_Active state, 0b otherwise.
This bit must be implemented if the corresponding Data
Link Layer Active Capability bit is implemented. Otherwise,
this bit must be hardwired to 0b.
Slot Clock Configuration (SCC):
0 = The device uses an independent clock irrespective of
the presence of a reference on the connector.
1 = The device uses the same physical reference clock that
the platform provides on the connector.
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