AC82G41SLGQ3 Datasheet, PDF (379/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.8.3
IDEPBMSR—IDE Primary Bus Master Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR4
2h
80h
RO, R/W, R/WC
8 bits
Reset: See bit definitions.
This register implements the Bus Master Status register of the primary channel.
Bit
Access
Default
Value
RST/PWR
Description
7
RO
1b
6
R/W
0b
5
R/W
0b
4:3
RO
00b
2
R/WC
0b
1
R/WC
0b
0
RO
0b
Core
Core
Core
Core
Core
Core
Core
Simplex Only (SO): Value indicates whether both Bus
Master Channels can be operated at the same time or not.
0 = Both can be operated independently
1 = Only one can be operated at a time.
Reset: ME System Reset
Drive 1 DMA Capable (D1DC): This bit is read/write by
the host (not write 1 clear).
Reset: Host system Reset or D3->D0 transition of the
function
Drive 0 DMA Capable (D0DC): This bit is read/write by
the host (not write 1 clear).
Reset: Host system Reset or D3->D0 transition of the
function
Reserved
Interrupt (INT): This bit is set by the hardware when it
detects a positive transition in the interrupt logic (refer to
IDE host interrupt generation diagram).The hardware will
clear this bit when the Host SW writes 1 to it.
Reset: ME System Reset
Error (ER): Bit is typically set by FW. Hardware will clear
this bit when the Host SW writes 1 to it.
Reset: ME System Reset
Bus Master IDE Active (BMIA): This bit is set by
hardware when SSBM register is set to 1 by the Host.
When the bus master operation ends (for the whole
command) this bit is cleared by FW. This bit is not cleared
when the HOST writes 1 to it.
Reset: ME system Reset
Datasheet
379