AC82G41SLGQ3 Datasheet, PDF (167/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.48
TSMICMD—Thermal SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CF1h
00h
RO, R/W
8 bits
This register selects specific errors to generate a SMI DMI special cycle, as enabled by
the Device 0 SMI Error Command Register [SMI on (G)MCH Thermal Sensor Trip]. The
SMI must not be enabled at the same time as the SERR/SCI for the thermal sensor
event.
All bits in this register are reset to their defaults by PLTRST#.
Bit
Access
Default
Value
RST/PWR
Description
7:3
RO
00h
Core
Reserved
SMI on (G)MCH Catastrophic Thermal Sensor Trip
(SMGCTST):
2
R/W
0b
Core
1 = Does not mask the generation of an SMI DMI special
cycle on a catastrophic thermal sensor trip.
0 = Disable reporting of this condition via SMI messaging.
SMI on (G)MCH Hot Thermal Sensor Trip
(SMGHTST):
1
R/W
0b
Core
1 = Does not mask the generation of an SMI DMI special
cycle on a Hot thermal sensor trip.
0 = Disable reporting of this condition via SMI messaging.
SMI on (G)MCH Aux Thermal Sensor Trip
(SMGATST):
0
R/W
0b
Core
1 = Does not mask the generation of an SMI DMI special
cycle on an Auxiliary thermal sensor trip.
0 = Disable reporting of this condition via SMI messaging.
Datasheet
167