AC82G41SLGQ3 Datasheet, PDF (484/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
Default
Value
RST/PWR
Description
5:0
W
Address Mask (AM): The value in this field specifies the
number of low order bits of the ADDR field that must be
masked for the invalidation operation. Mask field enables
software to request invalidation of contiguous mappings for
size-aligned regions. For example: Mask Value ADDR bits
masked Pages invalidated.
Mask Value Addr bits masked Pg inval
0
Nil
1
1
12
2
0s
Core
2
13:12
4
3
14:12
8
4
15:12
16
5
16:12
32
6
17:12
64
7
18:12
128
8
19:12
256
Hardware implementations report the maximum supported
mask value through the Capability register.
Value returned on read of this field is undefined.
484
Datasheet