AC82G41SLGQ3 Datasheet, PDF (403/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.10.7 KTFCR—KT FIFO Control Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/KT MM/IO
2h
00h
WO
8 bits
Reset: Host System Reset or D3->D0 transition
When Host writes to this address, it writes to the KTFCR. The FIFO control Register of
the serial interface is used to enable the FIFOs, set the receiver FIFO trigger level and
clear FIFOs under the direction of the Host.
When Host reads from this address, it reads the KTIIR.
Bit
Access
Default
Value
RST/PWR
Description
7:6
WO
5:4
WO
3
WO
2
WO
1
WO
0
WO
Receiver Trigger Level (RTL): Trigger level in bytes for
the RCV FIFO. Once the trigger level number of bytes is
reached, an interrupt is sent to the Host.
00b
Core
00 = 01
01 = 04
10 = 08
11 = 14
00b
Core
Reserved
0b
Core
RDY Mode (RDYM): This bit has no affect on hardware
performance.
XMT FIFO Clear (XFIC): When the Host writes one to this
0b
Core
bit, the hardware will clear the XMT FIFO. This bit is self-
cleared by hardware.
RCV FIFO Clear (RFIC): When the Host writes one to this
0b
Core
bit, the hardware will clear the RCV FIFO. This bit is self-
cleared by hardware.
FIFO Enable (FIE): When set, this bit indicates that the
0b
Core
KT interface is working in FIFO node. When this bit value is
changed the RCV and XMT FIFO are cleared by hardware.
Datasheet
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