AC82G41SLGQ3 Datasheet, PDF (115/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.31
Note:
TOUUD—Top of Upper Usable DRAM
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
A2-A3h
0000h
R/W/L
16 bits
This 16 bit register defines the Top of Upper Usable DRAM.
Configuration software must set this value to TOM minus all EP stolen memory if
reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit + 1byte
64 MB aligned since reclaim limit is 64M B aligned. Address bits 19:0 are assumed to
be 000_0000h for the purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is less than the value
programmed in this register and greater than or equal to 4 B.
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
15:0
Access
R/W/L
Default
Value
0000h
RST/PWR
Description
Core
TOUUD (TOUUD): This register contains bits 35:20 of an
address one byte above the maximum DRAM memory
above 4 GB that is usable by the operating system.
Configuration software must set this value to TOM minus
all EP stolen memory, if reclaim is disabled. If reclaim is
enabled, this value must be set to reclaim limit 64 MB
aligned since reclaim limit + 1byte is 64 MB aligned.
Address bits 19:0 are assumed to be 000_0000h for the
purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the
incoming address is less than the value programmed in this
register and greater than 4 GB.
Datasheet
115