AC82G41SLGQ3 Datasheet, PDF (105/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.21
Note:
PAM3—Programmable Attribute Map 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
93h
00h
RO, R/W/L
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from
0D0000h–0D7FFFh.
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
Access
Default
Value
RST/PWR
Description
7:6
RO
00b
5:4
R/W/L
00b
3:2
RO
00b
1:0
R/W/L
00b
Core
Core
Core
Core
Reserved
0D4000h-0D7FFFh Attribute (HIENABLE): This field
controls the steering of read and write cycles that
address the BIOS area from 0D4000 to 0D7FFF.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes
are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
Reserved
0D0000h-0D3FFFh Attribute (LOENABLE): This field
controls the steering of read and write cycles that address
the BIOS area from 0D0000h to 0D3FFFh.
00 = DRAM Disabled: Accesses are directed to DMI.
01 = Read Only: All reads are serviced by DRAM. All writes
are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are
serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are
serviced by DRAM.
Datasheet
105