AC82G41SLGQ3 Datasheet, PDF (60/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

System Address Map
3.1.5
Table 6.
3.1.6
3.2
System BIOS Area (F_0000h–F_FFFFh)
This area is a single 64 KB segment (000F_0000h – 000F_FFFFh). This segment can be
assigned read and write attributes. It is, by default (after reset), Read/Write disabled
and cycles are forwarded to the DMI Interface. By manipulating the Read/Write
attributes, the (G)MCH can “shadow” BIOS into the main DRAM. When disabled, this
segment is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
System BIOS Area Memory Segments
Memory Segments Attributes Comments
0F0000h – 0FFFFFh
WE RE
BIOS Area
PAM Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory
Area.
The (G)MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be
IWB cycles targeting DMI. However, DMI becomes the default target for processor and
DMI originated accesses to disabled segments of the PAM region. If the MTRRs covering
the PAM regions are set to WB or RD, it is possible to get IWB cycles targeting DMI.
This may occur for processor-originated cycles (in a DP system) and for DMI-originated
cycles to disabled PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.
Since the PAM region is “Read Disabled” the default target for the Memory Read
becomes DMI. The IWB associated with this cycle will cause the (G)MCH to hang.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Main Memory Address Range (1MB – TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that is
permitted to be accessible by the (G)MCH (as programmed in the TOLUD register). All
accesses to addresses within this range will be forwarded by the (G)MCH to the DRAM
unless it falls into the optional TSEG, or optional ISA Hole, or optional IGD stolen VGA
memory.
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