AC82G41SLGQ3 Datasheet, PDF (153/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.36
EPDCYCTRKWRTWR—EPD CYCTRK WRT WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A20-A21h
0000h
R/W, RO
16 bits
Bit
Access
15:12
R/W
11:8
7:4
3:0
R/W
RO
R/W
Default
Value
0h
0h
0h
0h
RST/PWR
Description
Core
Core
Core
Core
ACT To Write Delay (C0sd_cr_act_wr): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the ACT and WRITE commands to the same rank-
bank.
Same Rank Write To Write Delayed
(C0sd_cr_wrsr_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
Reserved
Same Rank WRITE to READ Delay (C0sd_cr_rd_wr):
This field indicates the minimum allowed spacing (in DRAM
clocks) between the WRITE and READ commands to the
same rank.
5.2.37
EPDCYCTRKWRTREF—EPD CYCTRK WRT REF
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR
A22-A23h
0000h
RO, R/W
16 bits
0h
EPD CYCTRK WRT ACT Status Register.
Bit
15:13
12:9
8:0
Access
RO
RO
R/W
Default
Value
RST/PWR
Description
000b
0h
000000000b
Core
Core
Reserved
Reserved
Different Rank REF to REF Delayed
(C0sd_cr_rfsh_rfsh): This field indicates the minimum
allowed spacing (in DRAM clocks) between two REF
commands to different ranks.
Datasheet
153