AC82G41SLGQ3 Datasheet, PDF (195/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
Bit
Access
Default
Value
RST/PWR
Description
Power State (PS): This field indicates the current power
state of this device and can be used to set the device into
a new power state. If software attempts to write an
unsupported state to this field, write operation must
complete normally on the bus, but the data is discarded
and no state change occurs.
00 = D0
01 = D1 (Not supported)
10 = D2 (Not supported)
11 = D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the
1:0
R/W
00b
Core
target of PCI configuration transactions (for power
management control). This device also cannot generate
interrupts or respond to MMR cycles in the D3 state. The
device must return to the D0 state in order to be fully-
functional.
When the Power State is other than D0, the bridge will
Master Abort (i.e. not claim) any downstream cycles (with
exception of type 0 config cycles). Consequently, these
unclaimed cycles will go down DMI and come back up as
Unsupported Requests, which the MCH logs as Master
Aborts in Device 0 PCISTS[13]
There is no additional hardware functionality required to
support these Power States.
6.1.27
SS_CAPID—Subsystem ID and Vendor ID Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
88-8Bh
0000800Dh
RO
32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides.
Because this device is an integrated part of the system and not an add-in device, it is
anticipated that this capability will never be used. However, it is necessary because
Microsoft will test for its presence.
Bit
31:16
15:8
Access
RO
RO
7:0
RO
Default
Value
0000h
80h
0Dh
RST/PWR
Description
Core
Core
Core
Reserved
Pointer to Next Capability (PNC): This field contains a
pointer to the next item in the capabilities list which is the
PCI Power Management capability.
Capability ID (CID): Value of 0Dh identifies this linked
list item (capability structure) as being for SSID/SSVID
registers in a PCI-to-PCI Bridge.
Datasheet
195