AC82G41SLGQ3 Datasheet, PDF (182/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.11
SUBUSN1—Subordinate Bus Number
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1Ah
00h
R/W
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express.
Bit
Access
Default
Value
RST/PWR
Description
Subordinate Bus Number (BUSN): This register is
programmed by configuration software with the number of
7:0
R/W
00h
Core
the highest subordinate bus that lies behind the device 1
bridge. When only a single PCI device resides on the PCI
Express segment, this register will contain the same value
as the SBUSN1 register.
6.1.12
IOBASE1—I/O Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
1Ch
F0h
RO, R/W
8 bits
This register controls the processor to PCI Express I/O access routing based on the
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode, address bits
A[11:0] are treated as 0. Thus, the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
Bit
Access
Default
RST/
Value
PWR
Description
I/O Address Base (IOBASE): This field corresponds to
A[15:12] of the I/O addresses passed by bridge 1 to PCI
Express.
7:4
R/W
Fh
Core
BIOS must not set this register to 00h; otherwise, 0CF8h/
0CFCh accesses will be forwarded to the PCI Express
hierarchy associated with this device.
3:0
RO
0h
Core
Reserved
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