AC82G41SLGQ3 Datasheet, PDF (113/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.29
ESMRAMC—Extended System Management RAM Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
9Eh
38h
R/W/L, R/WC, RO
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space.
The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM
memory space that is above 1 MB.
Bit
Access
Default
Value
RST/PWR
Description
7
R/W/L
0b
6
R/WC
0b
5
RO
1b
4
RO
1b
Core
Core
Core
Core
Enable High SMRAM (H_SMRAME): Controls the SMM
memory space location (i.e., above 1 MB or below 1 MB)
When G_SMRAME is 1 and H_SMRAME is set to 1, the high
SMRAM memory space is enabled. SMRAM accesses within
the range 0FEDA0000h to 0FEDBFFFFh are remapped to
DRAM addresses within the range 000A0000h to
000BFFFFh. Once D_LCK has been set, this bit becomes
read only.
Invalid SMRAM Access (E_SMERR): This bit is set when
the processor has accessed the defined memory ranges in
Extended SMRAM (High Memory and T-segment) while not
in SMM space and with the D-OPEN bit = 0. It is software's
responsibility to clear this bit. The software must write a 1
to this bit to clear it.
SMRAM Cacheable (SM_CACHE): This bit is forced to 1
by the (G)MCH.
L1 Cache Enable for SMRAM (SM_L1): This bit is forced
to 1 by the (G)MCH.
3
RO
1b
Core
L2 Cache Enable for SMRAM (SM_L2): This bit is
forced to 1 by the (G)MCH.
Datasheet
113