AC82G41SLGQ3 Datasheet, PDF (599/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Testability
16 Testability
In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has
been implemented as both JTAG boundary scan and XOR chains.
16.1 JTAG Boundary Scan
Figure 22.
The (G)MCH adds Boundary Scan ability compatible with the IEEE 1149.1-2001
Standard (Test Access Port and Boundary-Scan Architecture) specification. Refer to the
above mentioned specification for functionality. See Figure 22 for test mode entry.
JTAG Boundary Scan Test Mode Initialization Cycles
bscantest
ddpc_ctrldata
sdvo_ctrldata
ddr3_dram_pwrok
cl_pwrok
cl_rstb
pwrok
= 1 µs
drive straps low
= 0 µs
= 1 µs
= 3 µs
(values not important here)
rstinb
hpl_clkinp
exp_clkp
hpl_clkinn
exp_clkn
jtag_tck
jtag_tms
clock running or stopped
=3 =1
cycles cycle
(Clock frequency not critical)
clock running or stopped
= 1 µs
=5
cycles
The BSCANTEST pin serves as a boundary-scan test strap. Assertion of this strap (low)
is required to disable glitch-masking logic; otherwise, boundary-scan control signals to
device pin are blocked.
The DDR3_DRAM_PWROK pin must be high for the ddr3_dramrstb pin boundary-scan
data to become valid. Note that this signal is only used on platforms where DDR3 is
enabled. On DDR2 platforms, if DDR3_DRAM_PWROK is held low, then the boundary-
scan data on the ddr3_dramrstb pin will be invalid.
Datasheet
599