AC82G41SLGQ3 Datasheet, PDF (369/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.15 IDCHOR1—IDE Cylinder High Out Register Device 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
5h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register is read by the Host if Device = 1. ME-Firmware writes to this register at
the end of a command of the selected device. When the host writes to the IDE Cylinder
High In Register (IDECHIR), this register is updated with that value.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Cylinder High Out DEV 1 (IDECHO1): Cylinder
High out register for Slave device.
10.6.16 IDECHIR—IDE Cylinder High In Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
5h
00h
R/W/V
8 bits
Reset: Host system Reset or D3->D0 transition
This register implements the Cylinder High register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDECHIR, IDECHOR0, IDECHOR1) are updated with the written
value.
Host read to this register address reads the IDE Cylinder High Out Register IDECHOR0
if DEV=0 or IDECHOR1 if DEV=1.
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Cylinder High Data (IDECHD): Cylinder High data
register for IDE command block.
Datasheet
369