AC82G41SLGQ3 Datasheet, PDF (95/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.14
Note:
GGC—GMCH Graphics Control Register (Intel^® 82Q45,
82Q43, 82B43, 82G45, 82G43, 82G41 GMCH Only)
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
52-53h
0030h
R/W/L, RO
16 bits
All the bits in this register are Intel TXT lockable (82Q45/82Q43 GMCH only).
Bit
15:12
11:8
Access
RO
Default
Value
0h
R/W/L
0h
RST/
PWR
Core
Core
Description
Reserved
GTT Graphics Memory Size (GGMS): This field is used to select
the amount of Main Memory that is pre-allocated to support the
Internal Graphics Translation Table. The BIOS ensures that
memory is pre-allocated only when Internal graphics is enabled.
GSM is assumed to be a contiguous physical DRAM space with
DSM, and BIOS needs to allocate a contiguous memory chunk.
Hardware will drive the base of GSM from DSM only using the GSM
size programmed in the register.
0000 = No memory pre-allocated.
0001 = No VT mode, 1 MB of memory pre-allocated for GTT.
0011 = No VT mode, 2 MB of memory pre-allocated for GTT
1001 = VT mode, 2 MB of memory pre-allocated for 1 MB of Global
GTT and 1 MB for Shadow GTT
1010 = VT mode, 3 MB of memory pre-allocated for 1.5 MB of
Global GTT and 1.5 MB for Shadow GTT (82Q45 GMCH
only)
1011 = VT mode, 4 MB of memory pre-allocated for 2 MB of Global
GTT and 2 MB for Shadow GTT. (82Q45 GMCH only)
NOTE: All unspecified encodings of this register field are reserved,
hardware functionality is not assured if used. This register
is locked and becomes Read Only when the D_LCK bit in
the SMRAM register is set.
Datasheet
95