AC82G41SLGQ3 Datasheet, PDF (144/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.23
C1CYCTRKWR—Channel 1 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
656-657h
0000h
R/W
16 bits
Bit
Access
15:12
R/W
11:8
R/W
7:4
R/W
3:0
R/W
Default
Value
0h
0h
0h
0h
RST/PWR
Description
Core
Core
Core
Core
ACT To Write Delay (C1sd_cr_act_wr): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the ACT and WRITE commands to the same rank-
bank. This field corresponds to tRCD_wr in the DDR
Specification.
Same Rank Write To Write Delayed
(C1sd_cr_wrsr_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between two WRITE
commands to the same rank.
Different Rank Write to Write Delay
(C1sd_cr_wrdr_wr): This field indicates the minimum
allowed spacing (in DRAM clocks) between two WRITE
commands to different ranks. This field corresponds to
tWR_WR in the DDR Specification.
READ To WRTE Delay (C1sd_cr_rd_wr): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the READ and WRITE commands. This field
corresponds to tRD_WR in the DDR specification.
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Datasheet