AC82G41SLGQ3 Datasheet, PDF (355/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.5.13 SS—Sub System Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
2C-2Fh
00008086h
R/WO
32 bits
Reset: Host System Reset
These registers are used to uniquely identify the add-in card or the subsystem that the
device resides within.
Bit
31:16
15:0
Access
R/WO
R/WO
Default
Value
0000h
8086h
RST/PWR
Description
Core
Core
Subsystem ID (SSID): This is written by BIOS. No
hardware action taken on this value
Subsystem Vendor ID (SSVID): This is written by BIOS.
No hardware action taken on this value
10.5.14 EROM—Expansion ROM Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
30-33h
00000000h
RO
32 bits
This optional register is not implemented.
Bit
31:11
10:1
0
Access
RO
RO
RO
Default
Value
000000h
000h
0b
RST/PWR
Description
Core
Core
Core
Expansion ROM Base Address (ERBAR):
Reserved
Enable (EN): Enable expansion ROM Access.
10.5.15 CAP—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
34h
C8h
RO
8 bits
This optional register is used to point to a linked list of new capabilities implemented by
the device.
Bit
Access
Default
Value
RST/PWR
Description
7:0
RO
Capability Pointer (CP): This field indicates that the first
c8h
Core
capability pointer is offset C8h (the power management
capability).
Datasheet
355