AC82G41SLGQ3 Datasheet, PDF (430/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.1.3
ECAP_REG—Extended Capability Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/VC0PREMAP
10-17h
0000000000001000h
RO
64 bits
This register reports DMA-remapping hardware extended capabilities
Bit
63:24
Access
RO
23:20
RO
19:18
RO
17:8
RO
7
RO
6
RO
5
RO
4
RO
Default
Value
0s
0000b
00b
010h
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
Maximum Handle Mask Value (MHMV): The value in
this field indicates the maximum supported value for the
Handle Mask (HM) field in the interrupt entry cache
invalidation descriptor (iec_inv_dsc).
This field is valid only when the IR field is reported as Set.
Reserved
Invalidation Unit Offset (IVO): This field specifies the
location to the first IOTLB invalidation unit relative to the
register base address of this DMA-remapping hardware
unit.
If the register base address is X, and the value reported in
this field is Y, the address for the first IOTLB invalidation
unit is calculated as X+(16*Y).
If N is the value reported in NIU field, the address for the
last IOTLB invalidation unit is calculated as
X+(16*Y)+(16*N).
Snoop Control (SC):
0 = Hardware does not support 1-setting of the SNP field
in the page-table entries.
1 = Hardware supports the 1-setting of the SNP field in the
page-table entries.
Pass Through (PT):
0 = Hardware does not support passthrough translation
type in context entries.
1 = Hardware supports pass-through translation type in
context entries.
Caching Hints (CH):
0 = Hardware does not support IOTLB caching hints (ALH
and EH fields in context-entries are treated as
reserved).
1 = Hardware supports IOLTB caching hints through the
ALH and EH fields in context-entries.
Extended Interrupt Mode (EIM):
0 = Hardware supports only 8-bit APICIDs (Legacy
Interrupt Mode) on Intel^®64 and IA-32 platforms and
16- bit APIC-IDs on Itanium™ platforms.
1 = Hardware supports Extended Interrupt Mode (32-bit
APIC-IDs) on Intel^®64 platforms.
This field is valid only when the IR field is reported as Set.
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