AC82G41SLGQ3 Datasheet, PDF (194/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-PCI Express* Registers (D1:F0)
6.1.26
PM_CS1—Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/1/0/PCI
84-87h
00000008h
RO, R/W/P, R/W
32 bits
Bit
31:16
15
14:13
12:9
Access
RO
RO
RO
RO
8
R/W/P
7:4
RO
3
RO
2
RO
Default
Value
0000h
0b
00b
0h
0b
0000b
1b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Reserved: Not Applicable or Implemented. Hardwired to 0.
PME Status (PMESTS): This bit indicates that this device
does not support PMEB generation from D3cold.
Data Scale (DSCALE): This bit indicates that this device
does not support the power management data register.
Data Select (DSEL): This bit indicates that this device
does not support the power management data register.
PME Enable (PMEE): This bit indicates that this device
does not generate PMEB assertion from any D-state.
0 = PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
Reserved
No Soft Reset (NSR): When set to 1 this bit indicates
that the device is transitioning from D3hot to D0 because
the power state commands do not perform a internal
reset. Configuration context is preserved. Upon transition
no additional operating system intervention is required to
preserve configuration context beyond writing the power
state bits.
When clear the devices do not perform an internal reset
upon transitioning from D3hot to D0 via software control
of the power state bits.
Regardless of this bit the devices that transition from a
D3hot-to-D0 by a system or bus segment reset will return
to the device state D0 unintialized with only PME context
preserved if PME is supported and enabled.
Reserved
194
Datasheet